The present invention relates to chemical mechanical polishing (CMP), and in particular to optimized surface morphologies for polishing pads used in CMP apparatus.
In the fabrication of integrated circuits and other electronic devices, multiple layers of conducting, semiconducting, and dielectric materials are deposited on or removed from a surface of a semiconductor wafer. Thin layers of conducting, semiconducting, and dielectric materials may be deposited by a number of deposition techniques. Common deposition techniques in modem processing include physical vapor deposition (PVD), also known as sputtering, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), and electrochemical plating (ECP).
As layers of materials are sequentially deposited and removed, the uppermost surface of the substrate may become non-planar and require planarization. Planarizing a surface, or “polishing” a surface, is a process where material is removed from the surface of the wafer to form a generally even, planar surface. Planarization is useful in removing undesired surface topography and surface defects, such as rough surfaces, agglomerated materials, crystal lattice damage, scratches, and contaminated layers or materials. Planarization is also useful in forming features on a substrate by removing excess deposited material used to fill the features and to provide an even surface for subsequent processing.
Chemical mechanical planarization, or chemical mechanical polishing (CMP), is a common technique used to planarize substrates such as semiconductor wafers. In conventional CMP, a wafer carrier or polishing head is mounted on a carrier assembly and positioned in contact with a polishing pad in a CMP apparatus. The carrier assembly provides a controllable pressure that urges the substrate against the polishing pad. The pad is optionally moved (e.g., rotated) relative to the substrate by an external driving force. Simultaneously therewith, a chemical composition (“slurry”) or other fluid medium is flowed onto the polishing pad and between the substrate and the polishing pad. The substrate surface is thus polished by the chemical and mechanical action of the pad surface and slurry in a manner that selectively removes material from the substrate surface.
During the polishing process, the polishing pad is “conditioned”—i.e., is treated by a pad conditioner—so that the pad surface characteristics are maintained. Without pad conditioning, the polishing pad surface characteristics change with time. As the polishing pad surface is initially conditioned for optimal polishing, alteration of the pad surface during polishing results in a loss of polishing efficiency and is generally considered undesirable.
The polishing efficiency in CMP is dictated by several polishing parameters, namely: pressure between the substrate and polishing pad, the nature of the slurry, the relative rotational speed of the substrate and polishing pad, the nature of the substrate surface, and the nature of the polishing pad surface.
Here, “efficiency” qualitatively refers to the ability to reduce the step height on a wafer surface with the least amount of material removed. Quantitatively, planarization efficiency PE is defined as:                     PE        ≡                                            RR              High                        -                          RR              Low                                            RR            High                                              EQ        .                                   ⁢        1            wherein RRHigh is the removal rate of material from relatively high elevation features, and RRLow is the removal rate of material from relatively low elevation features. According to Equation 1, 0≦PE≦1.
FIG. 1 is a schematic close-up cross-sectional view of a polishing pad 10 having a surface 12 in contact with a substrate (hereinafter, “wafer”) 20 having a surface 22. Pad surface 12 has a surface shape (“morphology”) that is typically described as a “surface roughness.” Wafer surface 22 has low areas 30 and high areas 32 that give the surface a topography. In an example embodiment, low areas 20 and high areas 32 arise due to device structures (e.g., vias, trenches, interconnects, etc.) formed in the wafer during the formation of integrated circuits (ICs).
FIG. 2A is a plot of the idealized planarization efficiency. At the initial stage I of planarizing, low areas 30 do not contact the pad so that the removal rate for these areas (RRLow) is zero and PE=1. Further, during the intermediate stage II, both low and high areas 30 and 32 are contacted but the compression of the pad and the wafer step height dictate that RRHigh>RRLow, such that 0<PE<1. In the final stage III when the high areas have been effectively removed, the high and low rates are equal so that PE=0. In ideal planarization, the process goes from stage I to stage II essentially instantaneously so that the ideal PE curve is a step function.
In practice, areas of different effective density on the wafer get planarized at different rates, so that stage II is not infinitely short. In this case, the planarization efficiency (PE) curve has a slope during stage II, as illustrated in FIG. 2B. The time it takes for PE to drop significantly below 1 (i.e., the time it takes the process from transitioning from stage I to stage II is called the “induction time,” TI. It is typically preferable to have a relatively long induction time so that only the high areas of the wafer are polished, followed by a steep slope in stage II so that the low-lying areas on the wafer are polished as little as possible. Processes that are characterized by a long induction time will typically result in lower dishing and erosion on surfaces consisting of multiple materials, such as are encountered in the final stages of polishing shallow trench isolation and copper dual damascene structures.
Techniques have been put forth to increase polishing efficiency. For example, U.S. Pat. No. 6,497,613 to Meyer, entitled “Methods and apparatus for chemical mechanical planarization using a microreplicated surface,” describes polishing pad surface having a regular array of structures with sharp, distal apexes. The distal apexes contact the workpiece surface during polishing, whereby they ablate and become blunted. Thus, the planarization process starts out with aggressive polishing and a high removal rate, and finishes with a fine polishing and a low removal rate. This technique requires replacing the pad for each polishing operation, and is not amenable to a conditioning process that can maintain an optimized pad surface morphology.
Because of the large cost savings associated with planarizing surfaces as efficiently as possible, with as little loss of material as possible and with as little damage as possible, it is desirable to develop a polishing pad having a morphology that optimizes planarization performance, and methods for conditioning such pads to achieve and maintain the optimized morphology.